Increases in device packing densities have caused integrated circuits today to contain large quantities of both active and passive electronic devices, such as bipolar junction transistors (BJTs) or MOS devices. These devices must be electrically isolated and able to operate independently of each other to ensure so that the characteristics of individual devices remain constant despite operating conditions. Defective isolation between transistors, for example, may cause current leakage between the transistors. This leakage may result in a number of problems including latch-up (activation of a transistor as a result of feedback from neighboring transistors) and crosstalk as well as consuming a considerable amount of power. Thus, in fabrication of devices with exceedingly high (submicron) densities, electrical isolation with decreasing isolation width becomes of paramount importance.
Device isolation is usually accomplished using a few different techniques. One isolation technique uses selective/local oxidation of silicon (LOCOS), in which Si is thermally oxidized to produce lateral field oxide/SiO2 regions between the active devices. In general, the LOCOS process uses a pad oxide and pad nitride as a mask and defines the LOCOS area by photoresist masking and subsequent etching of the pad oxide, pad nitride, and Si substrate. After the etch, a relatively long thermal oxidation is used to fill the recessed Si areas with field oxide. The LOCOS process is cheap and simple, but has a number of problems including the fact that the lateral growth of the oxide results in a xe2x80x9cbird""s beakxe2x80x9d type structure which intrudes on neighboring active device structures and thereby decreases both the vertical uniformity of the structure and the precision of the isolation area. Besides these problems (e.g. the large height difference between the isolation regions and the active regions), other problems include redistribution of preimplanted dopants during heating to produce the field oxide, variations in local device and wafer level characteristics due to corresponding field oxide thickness variations between different isolation areas, and a limitation in the ultimate packing density of active devices/scalability of the integrated circuit while still effectively isolating the active devices. For these reasons and more, the LOCOS isolation technique is generally unacceptable for the increasingly complex and dense integrated circuits.
An alternate technique to isolate the active devices, motivated in part to overcome the deficiencies of the LOCOS process, is the shallow trench isolation (STI) method, which is better suited to the increased density structures due to the inherent scalability, planarity, and depth of the isolation. The STI method involves RIE (Reactive Ion Etching) etching a shallow trench in either the Si substrate or a semiconductor structure usually containing a pad oxide (SiO2) layer (and which may include a passivation layer composed of Si3N4) on the silicon substrate. For a very shallow Si-on-Insulator (SOI) wafer, the trench is etched 200-500 xc3x85 into the Si until the underlying buried oxide layer of the SOI wafer is reached. The trench is then filled conventionally by chemical vapor depositing (CVD) or, more recently, high-density plasma depositing (HDP) dielectric insulating materials, and the entire trench and multiple layer semiconductor structure are subsequently planarized by chemical-mechanical polishing (CMP). For example, TEOS (Tetraethyloxysilane) and O2, deposited at 600-800xc2x0 C., may be used in the CVD process to fill the trench with SiO2. To further simplify the STI process, a hard CMP polishing pad using cerium oxide/surfactant process may be applied without the necessity of a photolithographic step.
One serious problem with the conventional STI methods is that they use CVD-deposited (or HDP) insulating materials, which are less dense than and of general lower quality than thermally grown oxides. In addition, during wet etching processes (usually HF etched), CVD and HDP oxides are more severely eroded than thermal oxides resulting in trenches being non-uniformly filled with oxide, and, in some cases, being devoid of oxide. An alternate solution is to coat the sidewalls of the trench by thermally growing an oxide layer. This alternate solution, however, causes the active structure surrounding the trench containing Si to be consumed and creates the problem of intrusion onto the active structure surrounding the trench, similar to the bird""s beak problem.
It is thus more advantageous to replace the CVD and HDP oxides by thermal oxides that do not consume the silicon trench sidewalls to solve some of these problems. To this end a relatively new process has been developed in which undoped amorphous or polycrystalline Si is deposited in the trench rather than CVD or HDP-deposited SiO2. The undoped amorphous or polycrystalline Si is then heat-treated in an oxidation ambient to produce SiO2. In some cases, a thin layer of SiO2 is grown prior to deposition of the polysilicon. After oxidation of the polysilicon, the trench is over-filled and a layer of thermally grown SiO2 coats the active semiconductor area. The entire structure, including both the active semiconductor area and the filled trench, is subsequently planarized by a chemo-mechanical polishing process (CMP). The replacement of the CVD or HDP oxides has an immediate benefit to reduce the erosion encountered in wet etching after the STI process.
A typical process is shown in FIGS. 1A-1E. In FIG. 1A, a trench 102 is etched in the Si3N4/thin thermal SiO2 passivation layer structure and into the Si to form an active Si area 101 adjacent to the trench 102. In FIG. 1B, a thin (for example, 50 xc3x85) layer 103 of SiO2 is grown from the exposed Si in the trench 102. Next, in FIG. 1C, a thicker polysilicon layer 104 of a few hundred angstroms is deposited over the thin oxide layer 103 located at the trench sidewalls. This polysilicon layer 104 is subsequently heat-treated in an oxidation ambient to produce a resultant thicker thermally grown oxide layer 105 while consuming the original polysilicon layer 104, as shown in FIG. 1D. The resultant thermally grown oxide layer 105 overfills the trench 102 (i.e. extends higher than the upper level of the Si3N4 passivation layer structure adjacent to the trench) as well as covers the surface of the thin oxide layer 103 on the active Si area 101 adjacent to the trench 102. The resultant thermally grown oxide layer 105 is then selectively removed by CMP from the surface of the Si3N4 passivation layer structure adjacent to the trench 102 and the overfill of the thermally grown oxide layer 105 in the trench 102 is then removed, i.e. the structure is planarized, as illustrated in FIG. 1E.
However, despite the improvement in device characteristics and partial mitigation of the common problems faced using the LOCOS technique described above, the conventional STI methods only help to diminish these problems, they do not alleviate them entirely. Further, current process tolerances using the conventional STI methods are approximately 200 xc3x85, and cannot guarantee sufficient trench fill without having excessive step height between the oxide filling the trench and the active area adjacent to the trench. For thin SOI wafers, the process thickness tolerances of either of the CVD or HDP oxides and the hard mask cerium oxide/surfactant CMP planarizing process discussed above present a severe problem. Thus, a controllable process using a thermal oxide is necessary to assuage these general, remaining problems, which include those relating to the reduction of active device area (i.e. bird""s beak formation-type problems).
To solve these problems, a method of isolating active devices using shallow trench isolation has been developed having increased process control and using a thermally grown oxide. The method uses selective oxidation and does not result in reduction of active device area or extensive bird""s beaks formations. The use of a silicon-on-insulator substrate for active device isolation helps to further diminish the above problems. In all of the embodiments presented, the shallow trench is plugged with a thermal oxide, rather than a CVD deposited oxide.
A first aspect of the present invention is thus directed towards a method for forming an isolation trench in a semiconductor structure in which a trench is formed on a silicon-on-insulator substrate and an undoped polysilicon layer is deposited on the bottom and sidewalls of the trench and on the surface of the region adjacent to the trench. A substantial portion of the trench is left unfilled by the undoped polysilicon layer deposited. The polysilicon layer is thermally oxidized to form a thermal oxide that fills the trench and thereby avoids forming a birds-beak formation of the thermal oxide above the sidewalls of the trench.
The semiconductor structure may contain a multiple layer structure of Si, SiO2, and SiN layers. The sidewalls of the trench may also be covered with a thin thermal dielectric, such as an oxide, which is then treated with one of NO, N2O, and N ion implantation prior to depositing the undoped polysilicon layer.
The isolation structure, in addition, may be planarized. Planarization can be accomplished either by removing the polysilicon layer from the surface of the region adjacent to the trench before oxidation or, alternatively, by maintaining the polysilicon layer on the surface of the region adjacent to the trench but later removing the oxide from the SiN layer and adjusting height of the oxide in the trench.
A doped layer comprising doped polysilicon or doped SiO2 may additionally be formed above the silicon nitride layer before the undoped polysilicon layer is deposited. In this case, the isolation structure may then be heat treated prior to oxidization to drive dopants from the doped layer into the undoped polysilicon layer, thereby forming a secondarily doped polysilicon layer from the undoped polysilicon layer. Afterwards, prior to oxidation, selective wet etching removes the doped layers and exposes the silicon nitride layer.
These and other features and advantages of the invention will become apparent upon a review of the following detailed description of the presently preferred embodiments of the invention, when viewed in conjunction with the appended drawings.